In many systems on a chip (SoCs) today, high speed serial links are used to communicably connect two chips, such as, application processor, modem processor, etc. A common type of high speed serial link used in SoCs is serializer/deserializer (SerDes). A SerDes interface typically provides a serializer on a transmitter side to serialize data from multiple parallel streams to allow transmission of the data serially over a transmission medium or wire. Conversely, on a receiver side, the SerDes interface typically provides a deserializer to deserialize the serial data received in multiple lanes in parallel so that the deserialized data can be forwarded to downstream circuitry for further processing in parallel. SerDes interface is a popular choice of chip-to-chip interface because SerDes interface can ease the competition for the limited number of input/output (I/O) ports on chips.
As mentioned above, incoming data at a conventional SerDes interface of a receiver involves multiple lanes in parallel. Each lane provides a clock data recovery (CDR) module to track and extract clock edges from the incoming data. The clock edge extracted can be used to sample the incoming data during deserialization of the incoming data within that lane. In other words, CDR in conventional SerDes interface is performed on a per-lane basis during normal operation.
However, one issue with the conventional SerDes interface is high power consumption, in particular, the power consumption in CDR. Significant resource is employed to extract the clock edge information from the incoming data in order to track differences that may exist between the transmitting clock domain and the receiving clock domain. Since each lane in a conventional SerDes interface performs its own CDR, the power consumption is multiplied by the number of lanes in the interface, for example, 16.
Accordingly, there is a need in the art to provide a CDR scheme in SerDes receiver interface that is more power efficient.